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CMOS PARALLEL FIFO WITH FLAGS 64 x 5
IDT72413
FEATURES:
* First-ln/First-Out Dual-Port memory--45MHz * 64 x 5 organization * Low-power consumption -- Active: 200mW (typical) * RAM-based internal structure allows for fast fall-through time * Asynchronous and simultaneous read and write * Expandable by bit width * Cascadable by word depth * Half-Full and Almost-Full/Empty status flags * High-speed data communications applications * Bidirectional and rate buffer applications * High-performance CMOS technology * Available in plastic DIP and SOIC * Industrial temperature range (-40C to +85C) is available
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascad-able in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. This device is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers anD graphics controllers. The IDT72413 is fabricated using IDTs high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS.
FUNCTIONAL BLOCK DIAGRAM
OUPUT ENABLE (OE)
DATA IN (D0-4 ) (MR) MASTER RESET INPUT READY SHIFT IN (IR)
FIFO INPUT STAGE
64 x 5 MEMORY ARRAY
FIFO OUTPUT STAGE
DATA OUT (Q0-4 )
(SO) INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC (OR)
SHIFT OUT OUPUT READY
(SI)
FLAG CONTROL LOGIC
HALF-FULL (HF)
ALMOST-FULL/ EMPTY (AF/E)
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc.
COMMERCIAL TEMPERATURE RANGE
2003
JULY 2003
1
DSC-2748/8
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE HF IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
ABSOLUTE MAXIMUM RATINGS(1)
Vcc AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR
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Symbol VTERM TSTG IOUT
Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current
Commercial -0.5 to +7.0 -55 to +125 -50 to +50
Unit V C mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PLASTIC DIP (P20-1, ORDER CODE: P) SOIC (SO20-2, ORDER CODE: SO) TOP VIEW
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Supply Voltage Commercial Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Commercial Min. 4.5 0 2.0 -- 0 Typ. 5.0 0 -- -- -- Max. 5.5 0 -- 0.8 70 Unit V V V V C
CAPACITANCE
(TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF
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GND VIH VIL (1) TA
NOTE: 1. Characterized values, not currently tested.
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
IDT72413 Commercial fIN = 45, 35, 25 MHz Max. -- 10 0.4
Symbol IIL IIH VOL
Parameter Low-Level Input Current High-Level Input Current Low-Level Output Current
VOH
High-Level Output Current
IOS (2) IHZ ILZ ICC(3,4)
Output Short-Circuit Current HIGH Impedance Output Current LOW Impedance Output Current Active Supply Current
Test Conditions VCC = Max., GND VI VCC VCC = Max., GND VI VCC VCC = Min. IOL (Q0-4) IOL (IR, OR) (1) IOL (HF, AF/E) VCC = Min. IOH (Q0-4) IOH (IR, OR) IOH (HF, AF/E) VCC = Max. VO = 0V VCC = Max. VO = 2.4V VCC = Max. VO = 0.4V VCC = Max., OE = HIGH Inputs LOW, f = 25MHz
24 mA 8mA 8mA -4mA -4mA -4mA
Min. -10 -- --
Unit A A V
2.4
--
V
-20 -- -20 --
-110 20 -- 60
mA A A mA
NOTES: 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25MHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. Tested with outputs open (IOUT = 0). 4. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f -25MHz]) commercial.
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
OPERATING CONDITIONS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
IDT72413L45 Min. Max. 9 -- 11 -- 0 -- 13 -- 9 -- 11 -- 20 -- 20 -- Commercial IDT72413L35 Min. Max. 9 -- 17 -- 0 -- 15 -- 9 -- 17 -- 30 -- 35 -- IDT72413L25 Min. Max. 16 -- 20 -- 0 -- 25 -- 16 -- 20 -- 35 -- 35 --
Symbol tSIH(1) tSIL(1) tIDS tIDH tSOH(1) tSOL tMRW tMRS
Parameter Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI
Figure 2 2 2 2 5 5 8 8
Unit ns ns ns ns ns ns ns ns
NOTE: 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1F directly between VCC and GND with very short lead length is recommended.
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C)
Commercial Symbol fIN tIRL(1) tIRH(1) fOUT tORL(1) tORH(1) tODH(1) tODS tPT tMRORL tMRIRH(3) tMRIRL(2) tMRQ tMRHF tMRAFE tIPH(3) tOPH(3) tORD(3) tAEH tAEL tAFL tAFH tHFH tHFL tPHZ(3) tPLZ(3) tPLZ(3) tPHZ(3) Parameter Shift In Rate Shift In to Input Ready LOW Shift In to Input Ready HIGH Shift Out Rate Shift Out to Output Ready LOW Shift Out to Output Ready HIGH Output Data Hold Previous Word Output Data Shift Next Word Data Throughput or "Fall-Through" Master Reset to Output Ready LOW Master Reset to Input Ready HIGH Master Reset to Input Ready LOW Master Reset to Outputs LOW Master Reset to Half-Full Flag Master Reset to AF/E Flag Input Ready Pulse HIGH Output Ready Pulse HIGH Output Ready HIGH to Valid Data Shift Out to AF/E HIGH Shift In to AF/E Shift Out to AF/E LOW Shift In to AF/E HIGH Shift In to HF HIGH Shift Out to HF LOW Output Disable Delay Output Enable Delay Figure 2 2 2 5 5 5 5 5 4, 7 8 8 8 8 8 8 4 7 5 9 9 10 10 11 11 12 12 12 12 IDT72413L45 Min. Max. -- 45 -- 18 -- 18 -- 45 -- 18 -- 19 5 -- -- 19 -- 25 -- 25 -- 25 -- 25 -- 20 -- 25 -- 25 5 -- 5 -- -- 5 -- 28 -- 28 -- 28 -- 28 -- 28 -- 28 -- 12 -- 12 -- 15 -- 15 IDT72413L35 Min. Max. -- 35 -- 18 -- 20 -- 35 -- 18 -- 20 5 -- -- 20 -- 28 -- 28 -- 28 -- 28 -- 25 -- 28 -- 28 5 -- 5 -- -- 5 -- 28 -- 28 -- 28 -- 28 -- 28 -- 28 -- 12 -- 12 -- 15 -- 15 IDT72413L25 Min. Max. -- 25 -- 28 -- 25 -- 25 -- 28 -- 25 5 -- -- 20 -- 40 -- 30 -- 30 -- 30 -- 35 -- 40 -- 40 5 -- 5 -- -- 7 -- 40 -- 40 -- 40 -- 40 -- 40 -- 40 -- 15 -- 15 -- 20 -- 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1F directly between VCC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR forces IR to go LOW, and MR causes IR to go HIGH. 3. Guaranteed by design but not currently tested.
3
IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
STANDARD TEST LOAD DESIGN TEST LOAD 5V R1 OUTPUT
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AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
5V
2K
TEST POINT 30pF* 30pF*
R2
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or equivalent circuit *Including scope and jig
RESISTOR VALUES FOR STANDARD TEST LOAD
IOL 24mA 12mA 8mA R1 200 390 600 R2 300 760 1200
Figure 1. Output Load
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (OE) provides the capability of three-stating the FIFO outputs. FIFO RESET The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FIFO to enter an empty state signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Q0-4) will be LOW. DATA INPUT Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads input data into the first word location of the FIFO and causes the lnput Ready (IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved to the next word position and lR goes HlGH indicating the readiness to accept new data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.
DATA OUTPUT Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of SO. FALL-THROUGH MODE The FIFO operates in a Fall-Through Mode when data gets shifted into an empty FIFO. After the fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. A Fall-Through Mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO a location is available for new data. After a fallthrough delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one clock cycle) is far less than the delay of a Shift register-based FIFO.
SIGNAL DESCRIPTIONS: INPUTS:
DATA INPUT (D0-4) Data input lines. The IDT72413 has a 5-bit data input.
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
CONTROLS:
SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-4 lines. The data has to meet set-up and hold time requirements with respect to the rising edge of SI. SHIFT OUT (SO) Shift Out controls the outputs data from the FIFO. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. HALF-FULL FLAG (HF) Half-Full Flag signals when the FIFO has 32 or more words in it. INPUT READY (IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also used to cascade many FIFOs together, as shown in Figure 13.
OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. OR is also used to cascade many FIFOs together, as shown in Figure 13. OUTPUT ENABLE (OE) Output Enable is used to enable the FIFO outputs onto a bus. OE is active LOW. ALMOST-FULL/EMPTY FLAG (AF/E) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (Q0-4) Data output lines, three-state. The IDT72413 has a 5-bit output.
1/fIN tSIH SI tSIL
1/fIN
tIRH IR tIDS INPUT DATA
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tIDH
tIRL
Figure 2. Input Timing
SI
(7)
(2)
(4)
(1)
IR
(3)
(5) (6)
INPUT DATA
STABLE DATA
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NOTES: 1. IR HIGH indicates space is available and a SI pulse may be applied. 2. Input Data is loaded into the FIFO. 3. IR goes LOW indicating the FIFO is unavailable for new data. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full, then IR remains LOW. 7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Machanism of Shifting Data Into the FIFO
5
IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
(2)
COMMERCIAL TEMPERATURE RANGE
SO
(3)
SI tPT
(4)
(5)
tIPH
IR
(1)
INPUT DATA
STABLE DATA
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NOTES: 1. FIFO is initially full. 2. SO pulse is applied. 3. SI is held HIGH. 4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
SO
(7)
(2)
(4)
(1)
OR
(3) A or B
(5) (6)
OUTPUT DATA
A- DATA
B- DATA
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NOTES: 1. This data is loaded consecutively A, B, C. 2. Output data changes on the falling edge of SO after a valid SO sequence, i.e., OR and SO are both HIGH together.
Figure 5. Output TIming
1/fOUT tSOH SO tORD OR
(1)
1/fOUT tSOL
(2)
tRH
tODS tODH A-DATA
tORL B-DATA C-DATA
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OUTPUT DATA
NOTES: 1. OR HIGH indicates that data is available and a SO pulse may be applied. 2. SO goes HIGH causing the next step. 3. OR goes LOW. 4. Read pointer is incremented. 5. OR goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns. 6. If the FIFO has only one word loaded (A DATA) , OR stays LOW and the A-DATA remains unchanged at the outputs. 7. SO pulses applied when OR is LOW will be ignored.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
SI
SO tPT OR
(1)
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tOPH
NOTE: 1. FIFO initailly empty.
Figure 7. tPT and tOPH Specification
MR
(1)
tMRW tMRIRL tMRORL tMRIRH tMRS
IR
(1)
OR
SI tMRQ DATA OUTPUTS tMRHF HF tMRAFE AF/E
NOTE: 1. FIFO is partially full.
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Figure 8. Master Reset Timing
tSOH SO tAEH AF/E
(1)
tAEL tSIH SI
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NOTE: 1. FIFO contains 9 words (one more than Almost-Empty).
Figure 9. tAEH and tAEL Specifications
7
IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
COMMERCIAL TEMPERATURE RANGE
tSIH SI tHFH HF
(1)
tSOH SO
tHFL
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NOTE: 1. FIFO contains 55 words (one short of Almost-Full).
Figure 10. tAFH and tAFL Specifications
tSIH SI tHFH HF
(1)
tSOH SO
tHFL
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NOTE: 1. FIFO contains 31 words (one short of Half-Full).
Figure 11. tHFL and tHFH Specifications
3V OE tPZL WAVEFORM 1
(1)
VT
VT 0V 4.5V VT tPLZ 0.5V 1.5V VOL VOH 1.5V 0V 0.5V
2 74 8 d rw 14
t PZH WAVEFORM 2
(2)
tPHZ VT
NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. 2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Figure 12. Enable and Disable
8
IDT72413 CMOS PARALLEL FIFO WITH FLAGS 64 x 5
OUTPUT ENABLE HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR
COMMERCIAL TEMPERATURE RANGE
SHIFT OUT
COMPOSITE INPUT READY
HF IR SI D0 D1 D2 D3 D4
OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR
COMPOSITE OUTPUT READY
SHIFT IN
HF IR SI D0 D1 D2 D3 D4
OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR MASTER RESET
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NOTE: 1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs.
Figure 13. 64 x 15 FIFO with IDT72413
8-BITS SYSTEM 1 TWO IDT72413 64 x 8 SI SO IR OR
8-BITS SYSTEM 2
ENBL SI INTERRUPT
IO RDY INTERRUPT
ALMOST-FULL/ EMPTY HALF-FULL FLAG
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NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.
Figure 14. Application for IDT72413 for Two Asynchronous Systems
9
SHIFT IN INPUT READY
DATA IN
SI IR D0 D1 D2 D3 D4
MR
OR SO 0 Q Q1 Q2 Q3 Q4
SI IR D0 D1 D2 D3 D4
MR
OR SO 0 Q Q1 Q2 Q3 Q4
OUTPUT READY SHIFT OUT
DATA OUT
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NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.
MR
Figure 15. 128 x 5 Depth Expansion
ORDERING INFORMATION
IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK P SO 45 35 25 L Commercial (0C to +70C) Plastic DIP (300 mil, P20-1) Small Outline IC (300 mil, J-bend, SOIC SO20-2) Shift Frequency (fS) Speed in MHz
Commercial
Low Power
72413
NOTE: 1. Industrial temperature range is available by special order.
64 x 5 - FIFO
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DATASHEET DOCUMENT HISTORY
07/10/2003 pgs. 1, 2, 3, and 10. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
10
for Tech Support: 408-330-1753 email: FIFOhelp@idt.com

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